The present application has some Figures in common with, but is not necessarily otherwise related to, the following applications, which have common ownership and common effective filing dates with the present application: xe2x80x9cFast Frame Readout Architecture for Array Sensors with Integrated Correlated Double Sampling Systemxe2x80x9d Serial No. 60/070,083 filed Dec. 31, 1997; and xe2x80x9cSequential Correlated Doubling Sampling Technique for CMOS Area Array Sensorsxe2x80x9d Serial No. 60/070,082 filed Dec. 31, 1997, now U.S. Pat. No. 6,248,991; both of which are herein incorporated by reference.
The present application relates to CMOS imagers.
For the past 20 years or so, the field of optical sensing has been dominated by the charged couple device (xe2x80x9cCCDxe2x80x9d). However, CCD sensors have a number of problems associated with their manufacture and use. CCD imagers require a special manufacturing process which is incompatible with standard CMOS processing. Thus CCD imagers cannot be integrated with other chips that provide necessary support functions, but require independent support chips to perform, for example, CCD control, A/D conversion, and signal processing. The operation of a CCD imager also requires multiple high voltage supplies varying from, e.g. 5V to 12V. The higher voltages produce higher power consumption for CCD devices. Consequently, costs for both the CCD image sensor and ultimately the system employing the sensor, remain high.
The recent advances in CMOS technology have opened the possibility of imagers offering significant improvements in functionality, power, and cost of, for example, digital video and still cameras. Advances in chip manufacturing processes and reductions in supply voltages have encouraged revisitation of CMOS technology for use in image sensors. The advent of sub-micron CMOS technology allows pixels which contain several FETs, and are circuits in their own right, to be comparable in size to those existing on commercial CCD imagers. Fabrication on standard CMOS process lines permits these imagers to be fully integrated with digital circuitry to create single-chip camera systems. A CMOS area array sensor (or CMOS imager) can be fabricated with other system functions, e.g. controller, A/D, signal processor, and DSP. Hence, the cost of the CMOS process is more economical than that of the CCD process. CMOS imagers can operate with a single low supply voltage, e.g. 3.3V or 5V. This provides lower power consumption than CCD imagers.
One significant disadvantage with CMOS imagers has previously limited their widespread applicationxe2x80x94Fixed Pattern Noise (xe2x80x9cFPNxe2x80x9d). FPN is a built-in characteristic of X-Y addressable devices and is particularly an issue with any sort of CMOS imaging chips. FPN is noise that appears in a fixed pattern because the noise level is related to the position of the pixel in the array, the geometry of the column bus, and the proximity of other noise sources. (In addition, there is purely random noise not correlated to the pixel position, but due to inherent characteristics of the detector.) The effect of FPN is like viewing a scene through a window made of photo negatives. FPN occurs when process limitations produce device mismatches and/or non-uniformities of the sensor during fabrication on a wafer. FPN consists of both pixel FPN and column FPN. Each pixel circuit comprises at least a photodiode and a sensing transistor (operating as source-follower) as shown in FIG. 3. Mismatches of the sensing transistor between pixels may produce different output levels for a given input optical signal. The variations of these output levels is called pixel FPN. Additionally, each column (or row) has separate read circuitry. Driver mismatches between different columns (or rows) produce column FPN. Most device mismatches are caused by threshold voltage (VT) mismatches among CMOS transistors across the wafer.
A conventional solution for FPN suppression is to use a memory block to store the signal data for a whole frame and to subtract the FPN by sampling a reset voltage for the whole frame. The subtraction is done on a frame-by-frame basis which results in very slow frame rates.
Correlated Double Sampling (xe2x80x9cCDSxe2x80x9d) plays an important role in removing several kinds of noise in high-performance imaging systems. Basically, two samples of the sensor output are taken. First, a reference sample is taken that includes background noise and noise derived from a device mismatch. A second sample is taken of the background noise, device mismatch, and the data signal. Subtracting the two samples removes any noise which is common (or correlated) to both, leaving only the data signal. However, sensing the threshold voltage (VT) of the sensing transistor, is a problem. CDS is discussed in greater detail in a paper by Chris Mangelsdorf, Analog Devices, Inc., 1996 IEEE International Solid-State Circuits Conference, and is hereby incorporated by reference.
Mismatch Effects of a Non-ideal Pixel Reset Switch
No solutions currently exist for suppressing FPN caused by the mismatch effects of an NMOS reset switch in CMOS imagers. In silicon fabrication, an NMOS switching device with minimum size is normally used as the reset switch in order to obtain minimum pixel size for good image resolution, and to minimize parasitic capacitances. Variations in the device threshold voltages, VT, and sizes of the NMOS switching devices when fabricated in a wafer can be a large source of FPN. The effects are similar to the FPN caused by the variations of pixel-sensing NMOS transistors in a CMOS imager, without a Sequential CDS implementation (xe2x80x9cSCDSxe2x80x9d).
Mismatch-Independent Reset Sensing for CMOS Imagers
The present application discloses a technique for suppressing fixed pattern noise derived from a pixel reset switch. The Mismatch Independent Reset Sensing (xe2x80x9cMIRSxe2x80x9d) technique disclosed in this application enables reset-switch sensing in SCDS or CDS architectures to be independent of NMOS switching device variations. This is achieved by ensuring that the reset switch always operates in its linear region when turned ON. Therefore, even if mismatch effects exist in an NMOS reset switching device, the mismatch effect will not produce FPN on the pixel readout.
An advantage is that the reset switch mismatch effects in a CMOS area array sensor will not produce FPN at the output by using MIRS technique. Another advantage is that the MIRS, together with the SCDS technique, can suppress FPN from {fraction (1/25)} to {fraction (1/20)} the level when not implementing the innovative technique. Therefore, wide-spread application of CMOS imagers can be realized by using the SCDS/MIRS technique. Another advantage is that the technique can be easily integrated with other CDS techniques. Another advantage is that the innovative method provides a fully-integrated and low-cost solution to where a single chip incorporates all the necessary digital circuits for the CMOS imager system.